STCD2400 Datasheet, PDF (30/39 Pages) STMicroelectronics – Multichannel clock distribution circuit

DC and AC parameters
STCD22x0, STCD23x0, STCD24x0
Table 10. DC and AC characteristics (continued)
Sym.
Parameter
Condition⁽¹⁾
Min
Typ
Max
Unit
C_IN
I_OO
I_OI
V_ENH
V_ENL
V_OPTH
V_OPTL
Input capacitance
Output to output isolation
Output to input isolation
Enable voltage high⁽⁹⁾
Enable voltage low⁽⁹⁾
OPT pins voltage high
OPT pins voltage low
P_N
Additive phase noise^(3)(10)
t_JP
t_JC
t_RECB
Additive period jitter⁽³⁾
Additive cycle-cycle jitter⁽³⁾
Buffer recovery time from off to
on
For EN1-EN4
For EN1-EN4
For OPT1 and OPT2
For OPT1 and OPT2
at 1 kHz offset
at 10 kHz offset
at 100 kHz offset
rms value
rms value
STCD2xx0 active
t_RECC
STCD2xx0 recovery time from
standby to active (include LDO
wakeup time)
t_PD
Input to output propagation
delay⁽³⁾
Voltage transfer at 50%
C_L
R_L
Z_OUT
Capacitive load for each channel
Resistive load for each channel
Output impedance for each
channel
1.2
V_CC –0.3
10
3
45
45
V_CC
GND
–135
–145
–150
10
10
1
4
pF
dB
dB
V
0.6
V
V
GND+0.3 V
dBc/
Hz
ps
ps
10
µs
500
µs
3.5
6
ns
20
40
pF
kΩ
50
Ω
1. Valid for ambient operating temperature: T_A = –20 °C to 85 °C; V_CC = 2.5 V to 5.1 V; typical T_A = 25 °C;
load capacitance = 20 pF, f_MCLK = 26 MHz (except where noted).
2. Total accuracy includes line and load regulation, temperature and process condition. It does not include load and line
transients.
3. Simulated and determined via design and not 100% tested.
4. Ripple voltage = 0.1 Vpp.
5. Clock input voltage level should not exceed VTCXO voltage.
6. The rise time is measured when clock edge transfers from 10% V_CC to 90%V_CC. The fall time is measured when clock
edge transfers from 90%V_CC to 10%V_CC. The output rise/fall time is guaranteed for all input slew rates.
7. The quiescent current is measured when the enable pins are active, but with no input master clock signal (f_MCLK = 0 Hz).
8. The active current depends on the input master clock Vpp and frequency and the load condition. The typical test condition
is 26 MHz with 1.8 Vpp master clock input, C_L = 20 pF.
9. The test condition is V_ENH = 1.8 V and V_ENL = 0 V. When output enables simultaneously, there is no intentional skew in
design between the output clocks.
10. Guaranteed for all input clock slew rates.
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Doc ID 15400 Rev 2