TDA7500A Datasheet, PDF (28/40 Pages) STMicroelectronics – DIGITAL AM/FM SIGNAL PROCESSOR

TDA7500A
I²C TIMING
Figure 16. Definition of Timing for the I²C BUS.
Symbol
Parameter
Test Condition
F_SCL
t_BUF
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_R
t_F
t_SU;STO
t_SU:DAT
C_b
SCLl clock frequency
Bus free between a STOP and
Start Condition
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated start
condition
DATA hold time
Rise time of both SDA and SCL
signals
Fall time of both SDA and SCL
signals
Set-up time for STOP condition
Data set-up time
Capacitive load for each bus line
Cb in pF
Cb in pF
Standard Mode Fast Mode
I²C BUS
I²C BUS
Unit
Min. Max. Min. Max.
0
100
0
400 kHz
4.7
–
1.3
–
µs
4.0
–
0.6
–
µs
4.7
–
1.3
–
µs
4.0
–
0.6
–
µs
4.7
–
0.6
–
µs
0
–
0
0.9
µs
–
1000 20+ 300
ns
0.1C_b
–
300 20+ 300
ns
0.1C_b
4
–
0.6
–
µs
250
--
--
100
ns
–
400
–
400
pF
SPDIF TIMING
Symbol
Parameter
SPVL AC input level
SPIR Input impedance
SPHYS Hysteresis of input
Test Condition
@ 1 kHz
Min. Typ. Max. Unit
0.2
0.5
3.3 Vpp
–
6
–
kΩ
–
40
–
mV
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