TDA7500A Datasheet, PDF (24/40 Pages) STMicroelectronics – DIGITAL AM/FM SIGNAL PROCESSOR

TDA7500A
EXTERNAL MEMORY INTERFACE (EMI) DRAM MODE
Characteristics
Page Mode Cycle Time
RAS or RD Assertion to Data Valid
CAS Assertion to Data Valid
Column Address Valid to Data Valid
CAS Assertion to Data Active
RAS Assertion Pulse Width (Note 1)
(Page Mode Access Only)
RAS Assertion Pulse Width (Single Access Only)
RAS or CAS Negation to RAS Assertion
CAS Assertion Pulse Width
Last CAS Assertion to RAS Negation (Page Mode Access Only)
Note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6.
DRAM Refresh Timing
Characteristics
RAS Negation to RAS Assertion
CAS Negation to CAS Assertion
Refresh Cycle Time
RAS Assertion Pulse Width
RAS Negation to RAS Assertion for Refresh Cycle (Note 1)
CAS Assertion to RAS Assertion on Refresh Cycle
RAS Assertion to CAS Negation on Refresh Cycle
RAS Negation to CAS Assertion on a Refresh Cycle
CAS Negation to Data Not Valid
Note: 1. Happens when a Refresh Cycle is followed by an Access Cycle.
Timing
Mode
slow
fast
slow
fast
slow
fast
slow
fast
slow
fast
slow
fast
slow
fast
slow
fast
slow
fast
40MHz
Min.
Max.
10075
----
--
159
--
109
--
65
--
40
--
80
--
55
0
--
264
--
189
--
164
--
114
--
120
--
70
--
65
--
40
--
60
--
35
--
Timing
Mode
slow
fast
slow
fast
slow
fast
slowf
ast
slow
fast
slow
fast
slow
fast
40MHz
Min.
Max.
143
--
93
--
118
--
68
--
325
--
225
--
166
--
116
--
120
--
70
--
18
--
160
--
110
--
114
--
64
--
0
--
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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