TDA7500A Datasheet, PDF (26/40 Pages) STMicroelectronics – DIGITAL AM/FM SIGNAL PROCESSOR

TDA7500A
Figure 14. DRAM Read Cycle.
DRA [8:0]
RAS
Row address 1
Column address 1 ^{Column address 2 Row address 2}
CAS
DRD
DRD [3:0]
Figure 15. DRAM Write Cycle.
nibble 1
nibble 2
DRA [8:0]
RAS
Row address 1
Column address 1 Column address 2
Row address 2
CAS
DWR
DRD[3:0]
nibble 1
nibble 2
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