ST10F296E Datasheet, PDF (244/346 Pages) STMicroelectronics – High performance 16-bit CPU with DSP functions

Power reduction modes
ST10F296E
21.3 Standby mode
In stand-by mode, the RAM array is maintained powered through the dedicated pin, V_STBY,
when the main power supply (V_DD) of the ST10F296E is turned off.
To enter stand-by mode, the device must be held under reset. In this way, the RAM is
disabled (see XRAM2EN bit of XPERCON register, Table 5), and its digital interface is
frozen to avoid any kind of data corruption. It is then possible to turn off the main V_DD
provided that V_STBY is on.
A dedicated embedded low-power voltage regulator is implemented to generate the internal
low voltage supply to bias the portion of XRAM (16 Kbytes).
In normal running mode (when V_DD is on), the V_STBY pin can be tied to V_SS during reset, to
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exercise the EA functionality associated with the same pin. The voltage supply for the
circuits which are usually biased with V_STBY is granted by the active V_DD.
Standby mode can generate problems associated with the use of different power supplies in
CMOS systems. Particular attention must be paid when the ST10F296E I/O lines are
interfaced with other external CMOS integrated circuits. In standby mode, if the V_DD of the
device falls below that of the output level forced by the I/O lines of the external integrated
circuits, the device could be powered directly through the inherent diode existing on the
device output driver circuit. The same is valid for the ST10F296E when it is interfaced to
active/inactive communication buses during standby mode. Current injection can be
generated through the inherent diode.
In addition, the sequence of turning on/off the different voltages could be critical for the
system. The device standby mode current (I_STBY) may vary while the V_DD to V_STBY
transition occurs (and vice versa) as some current flows between the V_DD and V_STBY pins.
System noise on both the V_DD and V_STBY pins can increase this phenomenon.
Entering standby mode
To enter standby mode, the XRAM2EN bit in the XPERCON register must be cleared (this
bit is automatically reset by any kind of reset event, see Section 20: System reset). This
allows the RAM interface to be frozen immediately, thereby avoiding any data corruption. As
a consequence of a reset event, the RAM power supply is switched to the internal low-
voltage supply, V_18SB (derived from V_STBY through the low-power voltage regulator). The
RAM interface remains frozen until the XRAM2EN bit is set again by the software
initialization routine (at the next exit from V_DD power-on reset sequence).
When V₁₈ falls (as a result of V_DD being turning off), the XRAM2EN bit is no longer be able
to guarantee its content (logic 0), because the XPERCON register is powered by internal
V₁₈. This does not generate a problem because the standby mode switching dedicated
circuit continues to confirm that the RAM interface is freezing, irrespective of the XRAM2EN
bit content. The XRAM2EN bit status is considered once more when the internal V₁₈ starts
again and replaces the internal stand-by reference V_18SB.
If internal V₁₈ falls below the internal stand-by reference (V_18SB) by about 0.3 to 0.45 V
when the XRAM2EN bit is set, the RAM supply switching circuit is inactive. If there is a
temporary drop on the internal V₁₈ voltage versus internal V_18SB during normal code
execution, no spurious standby mode switching can occur (the RAM is not frozen and can
still be accessed).
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