ST10F296E Datasheet, PDF (237/346 Pages) STMicroelectronics – High performance 16-bit CPU with DSP functions

ST10F296E
System reset
20.9 Reset summary
Table 132 summarizes the different reset events.
Table 132. Reset events summary
Event
Min
RSTIN
Max
WDTCON flags
1 ms (VREG)
0 0 N Asynch. 1.2 ms (reson. + PLL)
-
10.2 ms (crystal + PLL)
t(s) ^{Power-on reset 0 1 N Asynch.}
1 ms (VREG)
-
11110
11110
1xx
Forbidden
uc _{x x Y}
Not applicable
rod ^{) 0 0 N Asynch.}
500 ns
-
01110
P _{t(s Hardware reset 0 1 N Asynch.}
te ^{c (asynchronous)} 0 0 Y Asynch.
500 ns
500 ns
-
01110
-
01110
le du _{0 1 Y Asynch.}
500 ns
-
01110
bso ^{Pro 1}
0 N Synch.
Max (4 TCL, 500 ns)
1032 + 12 TCL + max (4
TCL, 500 ns)
0
0
1
1
0
) ^{- O lete 1}
1 N Synch.
Max (4 TCL, 500 ns)
1032 + 12 TCL + max (4
TCL, 500ns)
0
0
1
1
0
t(s ^{o Short hardware}
c ^{bs reset}
(synchronous)⁽¹⁾
1
0
Y Synch.
Max (4 TCL, 500 ns)
1032 + 12 TCL + max (4
TCL, 500 ns)
0
0
1
1
0
u _{O Activated by internal logic for 1024 TCL}
Prod _t(s) ^- 1
1
Y Synch.
Max (4 TCL, 500 ns)
1032 + 12 TCL + max (4
TCL, 500 ns)
0
0
1
1
0
te ^{c Activated by internal logic for 1024 TCL}
sole ^{rodu 1}
0
N
Synch.
1032 + 12 TCL + max
(4 TCL, 500 ns)
-
01110
Ob _te ^P _{Long hardware}
le _reset
so ^{(synchronous)}
1
1
N
Synch.
1032 + 12 TCL + max(
4 TCL, 500 ns)
-
1032 + 12 TCL + max
1 0 Y Synch.
(4 TCL, 500 ns)
-
Activated by internal logic only for 1024 TCL
01110
01110
Ob ^{1032 + 12 TCL + max}
1 1 Y Synch.
(4 TCL, 500 ns)
-
01110
Activated by internal logic only for 1024 TCL
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