ST10F296E Datasheet, PDF (199/346 Pages) STMicroelectronics – High performance 16-bit CPU with DSP functions

ST10F296E
CAN modules
17.6 Configuration of the CAN controller
In the C-CAN and in most CAN implementations, the bit timing configuration is programmed
in two register bytes. The sum of Prop_Seg and Phase_Seg1 (as TSeg1) is combined with
Phase_Seg2 (as TSeg2) in one byte, and SJW and BRP are combined in the second byte.
In these bit timing registers (CANxBTR), the four components TSeg1, TSeg2, SJW, and
BRP have to be programmed to a numerical value that is one less than its functional value.
Therefore, instead of values in the range of [1...n], values are programmed in the range
[0...n-1]. Consequently, SJW (functional range of [1...4]) is represented by only two bits.
The length of the bit time is [TSeg1 + TSeg2 + 3] t_q (programmed values) or [Sync_Seg +
Prop_Seg + Phase_Seg1 + Phase_Seg2] t_q (functional values).
The data in the bit timing registers are the configuration input of the CAN protocol controller.
) The baud rate prescaler (configured by BRP) defines the length of the time quantum and the
t(s ^{basic time unit of the bit time. The bit timing logic (configured by TSeg1, TSeg2, and SJW)}
defines the number of time quanta in the bit time.
uc _{Processing of the bit time, calculation of the position of the sample point, and occasional}
d _{synchronizations are controlled by the bit timing logic (BTL) state machine, which is}
Pro _t(s) ^{evaluated once each time quantum. The rest of the CAN protocol controller, the bit stream}
processor (BSP) state machine, is evaluated once each bit time, at the sample point.
lete ^{uc The shift register serializes the messages to be sent and parallelizes received messages. Its}
d _{loading and shifting is controlled by the BSP.}
so ^ro The BSP translates messages into frames and vice versa. It generates and discards the
b ^P _{enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the cyclic}
- ^{O te redundancy check (CRC) code, performs the error management, and decides which type of}
) ^{le synchronization is to be used. It is evaluated at the sample point and processes the sampled}
t(s ^{o bus input bit. The time after the sample point that is needed to calculate the next bit to be}
s _{sent (for example, data bit, CRC bit, stuff bit, error flag, or idle) is called the information}
c ^b _{processing time (IPT).}
du _- ^O The IPT is application specific but may not be longer than 2 t_q. The C-CAN’s IPT is 0 t_q. Its
ro ^{) length is the lower limit of the programmed length of Phase_Seg2. In case of a}
P _t(s ^{synchronization, Phase_Seg2 may be shortened to a value less than IPT, which does not}
O_O^b_b^s_s^o_o^l_l^e_e^t_t^ee ^{Produc affect bus timing.}
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