ST10F296E Datasheet, PDF (223/346 Pages) STMicroelectronics – High performance 16-bit CPU with DSP functions

ST10F296E
System reset
Figure 79. Synchronous short/long hardware reset (EA = 1)
≤4 TCL⁽⁴⁾ ≤12 TCL
< 1032 TCL
RSTIN
(1)
≤≥55000nnss
RSTF
(after filter)
(3)
≤≥55000nnss
≤≥55000nnss
P0[15:13]
Not transparent
≤ 2 TCL
P0[12:2]
t(s) ^P0[1:0]
uc _IBUS-CS
d _(internal)
Pro _{t(s) FLARST}
lete duc _RST
bso ^Pro RSTOUT
Not t.
Transparent
Not transparent
≤1 ms
1024 TCL
8 TCL
Not t.
Not t.
7 TCL
At this time RSTF is sampled high or low
so it is a short or long reset
t(s) ^{- O solete RPD}
200 mA discharge
(2) _{VRPD > 2.5 V asynchronous reset not entered}
uc _{Ob 1. RSTIN assertion can be released here. See Section 21.1: Idle mode on page 240 for details on minimum pulse duration.}
rod ^{- 2. If RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation) during the reset condition (RSTIN low), an}
) _{asynchronous reset is entered immediately.}
P _t(s 3. The RSTIN pin is pulled low if the BDRSTEN bit (of the SYSCON register) was previously set by software. The BDRSTEN
bit is cleared after reset.
te ^{c 4. The minimum RSTIN low pulse duration must be longer than 500 ns, to guarantee the pulse is not masked by the internal}
O_O^b_b^s_s^o_o^l_l^e_ete ^{Produ filter (see Section 21.1: Idle mode on page 240).}
223/346