M36L0R7060U1 Datasheet, PDF (15/22 Pages) STMicroelectronics – 128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package

M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Functional description
Table 2. Operating modes - Standard Asynchronous operation
Operation^{(1) (2)}
WAIT
E_F G_F W_F RP_{F (3)}
L
Other
E_P W_P G_P UB_P LB_P CR_P A19 A18 Address
Inputs
ADQ0-
ADQ7
ADQ8-
ADQ15
Bus Read
V_IL V_IL V_IH V_IH
V_IH
Bus Write
V_IL V_IH V_IL V_IH
V_IH
Address Latch V_IL V_IH X V_IH
V_IL
Output
Disable
V_IL V_IH V_IH V_IH
V_IH
Standby
Reset
V_IH X X V_IH Hi-Z X
X X X V_IL Hi-Z X
Word Read
The PSRAM must be disabled.
Data Output
Data Input
Address Input
Any PSRAM mode is allowed.
V_IH V_IL V_IL V_IL V_IL Address In Valid
Hi-Z
Hi-Z
Hi-Z
Address In/ Data
Out Valid
Word Write
V_IL V_IH V_IL
\_/
Read
Configuration _{The Flash memory must}
Register (CR
be disabled.
controlled
method)⁽⁴⁾
V_IH V_IL V_IL
V_IL
Program
Configuration
Register (CR
Controlled)⁽⁵⁾
V_IL
V_IL V_IH X
V_IL V_IL Address In Valid
00(RCR)
V_IL
10(BCR)
X1(DIDR)
V_IH
0 or 00
(RCR)
X
1 or 10
(BCR)⁽⁶⁾
X
BCR/
RCR
Data
Address In/ Data In
Valid
Address In/ BCR,
RCR or DIDR
Content Valid
Address In Valid
Output
Disable/No
V_IH X X X V_IL X X
X
Operation
Deep Power-
Down⁽⁷⁾
Any Flash memory
mode is allowed.
X
V_IH X X X X X X X
X
High-Z
High-Z
Standby
V_IH X X X X X V_IL X
X
High-Z
1. The Clock signal, K, must remain Low when the PSRAM is operating in asynchronous mode.
2. X = Don’t Care
3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. Operating mode available in the M36L0R7060U1 and M36L0R7060L1 only (see M69KM096AA datasheet).
5. BCR and RCR only.
6. In the PSRAM of the M36L0R7050U1 and M36L0R7050L1, A19 is used to select between the BCR and the RCR whereas
in the PSRAM of the M36L0R7060U1 and M36L0R7060L1 both A18 and A19 are used to select the BCR, the RCR or the
DIDR.
7. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR
set to ‘0’. The device remains in Deep Power-Down mode until E goes Low again and is held Low for t_ELEH(DP).
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