M36L0R7060U1 Datasheet, PDF (11/22 Pages) STMicroelectronics – 128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package

M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Signal descriptions
2.6
Flash memory Chip Enable (E_F)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V_ILand Reset is at V_IH the device is in active
mode. When Chip Enable is at V_IH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the stand-by level.
It is not allowed to set both E_F and E_P to V_IL at the same time.
2.7
Flash memory Output Enable (G_F)
The Output Enable input controls data outputs during the Bus Read operation of the Flash
memory.
2.8
Flash memory Write Enable (W_F)
The Write Enable input controls the Bus Write operation of the Flash memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.9
Flash memory Write Protect (WP_F)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at V_IL, the Lock-Down is enabled and the protection status of the Locked-
Down blocks cannot be changed. When Write Protect is at V_IH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (refer to M58LRxxxGUL
datasheet).
2.10
2.11
Flash memory Reset (RP_F)
The Reset input provides a hardware reset of the memory. When Reset is at V_IL, the
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I_DD2. Refer to the M58LRxxxGUL datasheet for the
value of I_DD2. After Reset all blocks are in the Locked state and the Configuration Register is
reset. When Reset is at V_IH, the device is in normal operation. Exiting reset mode the device
enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is
required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V_RPH (refer to the M58LRxxxGUL datasheet).
PSRAM Chip Enable (E_P)
Chip Enable, E_P, activates the device when driven Low (asserted). When de-asserted (V_IH),
the device is disabled and goes automatically in low-power Standby mode or Deep Power-
Down mode, according to the RCR settings.
It is not allowed to set both E_F and E_P to V_IL at the same time.
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