M36L0R7060U1 Datasheet, PDF (12/22 Pages) STMicroelectronics – 128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package

Signal descriptions
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
2.12
PSRAM Output Enable (G_P)
When held Low, V_IL, the Output Enable, G_P, enables the Bus Read operations of the
memory.
2.13
PSRAM Write Enable (W_P)
Write Enable, W_P, controls the Bus Write operation of the memory. When asserted (V_IL), the
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
2.14
PSRAM Upper Byte Enable (UB_P)
The Upper Byte Enable, UB_P, gates the data on the Upper Byte of the Address Inputs/ Data
Inputs/Outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a
write or read operation.
2.15
2.16
PSRAM Lower Byte Enable (LB_P)
The Lower Byte Enable, LB_P, gates the data on the Lower Byte of the Address Inputs/Data
Input/Outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write
or read operation.
If both LB_P and UB_P are disabled (High), the device will disable the data bus from receiving
or transmitting data. Although the device will seem to be deselected, it remains in an active
mode as long as E_P remains Low.
PSRAM Configuration Register Enable (CR_P)
When this signal is driven High, V_IH, bus read or write operations access either the value of
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
2.17
V_DDF Flash memory Supply Voltage
V_DDF provides the power supply to the internal core of the Flash memory. It is the main
power supply for all Flash memory operations (Read, Program and Erase).
2.18
V_CCP PSRAM Supply Voltage
The V_CCP Supply Voltage is the core supply voltage.
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