M36L0R7060U1 Datasheet, PDF(14/22 Page) STMicroelectronics – 128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package

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M36L0R7060U1 Datasheet, PDF (14/22 Pages) STMicroelectronics – 128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package

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Functional description

M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1

Functional description

The PSRAM and Flash memory components have separate power supplies but share the

same grounds. They are distinguished by two Chip Enable inputs: EF for the Flash memory

and EP for the PSRAM.

Recommended operating conditions do not allow more than one device to be active at a

time. The most common example is simultaneous read operations on one of the Flash

memory and the PSRAM components which would result in a data bus contention.

Therefore it is recommended to put the other devices in the high impedance state when

reading the selected device.

Figure 3. Functional block diagram

A21-A22(1)

or A22(2)

RPF

WPF

VDDF VPPF VDDQF

128 Mbit

Flash

Memory

A16-A20(1)

or A16-A21(2)

VCCP

WAIT

VSS

ADQ0-ADQ15

CRP

UBP

LBP

32 Mbit

64 Mbit

PSRAM

1. Address Inputs corresponding to the M36L0R7050U1 and M36L0R7050L1 devices.

2. Address Inputs corresponding to the M36L0R7060U1 and M36L0R7060L1 devices.

AI12335

14/22

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