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S6E2H1 Datasheet, PDF (95/159 Pages) SPANSION – processor version | |||
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S6E2H1 Series
Multiplexed Bus Access Synchronous SRAM Mode
Parameter
MALE delay time
Symbol
tCHAL
tCHAH
Pin Name
MCLK,
ALE
MCLKââ
Multiplexed address delay time
tCHMADV
MCLKââ
Multiplexed data output time
tCHMADX
MCLK,
MADATA[15:0]
Conditions
VCC ⥠4.5 V
VCC < 4.5 V
VCC ⥠4.5 V
VCC < 4.5 V
VCC ⥠4.5 V
VCC < 4.5 V
VCC ⥠4.5 V
VCC < 4.5 V
Note:
â When the external load capacitance CL = 30 pF
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Min
Max
1
9
12
1
9
12
Unit Remarks
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 001-98940 Rev.*A
Page 95 of 159
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