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| S71WS512NE0BFWZZ Datasheet, PDF (87/142 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt | |||
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Advance Information
Program Command Sequence (last two cycles)
Read Status Data
VIH
CLK
VIL
AVD
Addresses
tAVD
tAS
tA
tAVS
tAVH
555h
Data
tCA
CE#
A0h
tDS
tD
PA
PD
VA
VA
In
Progress
Complete
OE#
tC
tW
WE#
tCS
tWPH
tWC
tWHWH1
tVC
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. âIn progressâ and âcompleteâ refer to status of program operation.
3. A23âA14 for the WS256N are donât care during command sequence unlock cycles.
4. CLK can be either VIL or VIH.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the
Configuration Register.
Figure 21. Asynchronous Program Operation Timings: WE# Latched Addresses
June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBit⢠Flash Family For Multi-chip Products (MCP)
87
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