S71WS512NE0BFWZZ Datasheet, PDF (102/142 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt

Preliminary
FUNCTIONAL DESCRIPTION (Continued)
CLK Input Function
The CLK is input signal to synchronize memory to microcontroller or system bus
frequency during synchronous burst read & write operation. The CLK input
increments device internal address counter and the valid edge of CLK is referred
for latency counts from address latch, burst write data latch, and burst read data
out. During synchronous operation mode, CLK input must be supplied except for
standby state and power down state. CLK is don’t care during asynchronous
operation.
ADV# Input Function
The ADV# is input signal to indicate valid address presence on address inputs. It
is applicable to synchronous operation as well as asynchronous operation. ADV#
input is active during CE#1=L and CE#1=H disables ADV# input. All the address
are determined on the positive edge of ADV#.
During synchronous burst read/write operation, ADV#=H disables all address
inputs. Once ADV# is brought to High after valid address latch, it is inhibited to
bring ADV# Low until the end of burst or until burst operation is terminated. ADV#
Low pulse is mandatory for synchronous burst read/write operation mode to latch
the valid address input.
During asynchronous operation, ADV#=H also disables all address inputs. ADV#
can be tied to Low during asynchronous operation and it is not necessary to control
ADV# to High.
WAIT# Output Function
The WAIT# is output signal to indicate data bus status when the device is operating
in synchronous burst mode.
During burst read operation, WAIT# output is enabled after specified time duration
from OE#=L. WAIT# output Low indicates data out at next clock cycle is invalid,
and WAIT# output becomes High one clock cycle prior to valid data out. During
OE# read suspend, WAIT# output doesn’t indicate data bus status but carries the
same level from previous clock cycle (kept High) except for read suspend on the
final data output. If final read data out is suspended, WAIT# output become high
impedance after specified time duration from OE#=H.
During burst write operation, WAIT# output is enabled to High level after specified
time duration from WE#=L and kept High for entire write cycles including WE#
write suspend. The actual write data latching starts on the appropriate clock edge
with respect to Valid Click Edge, Read Latency and Burst Length. During WE#
write suspend, WAIT# output doesn’t indicate data bus status but carries the
same level from previous clock cycle (kept High) except for write suspend on the
final data input. If final write data in is suspended, WAIT# output become high
impedance after specified time duration from WE#=H.
This device doesn’t incur additional delay against accrossing device-row boundary
or internal refresh orepation. Therefore, the burst operation is always started after
fixed latency with respect to Read Latency. And there is no waitting cycle asserted
in the middle of burst operation except for burst suspend by OE# brought to High
or WE# brought to High. Thus, once WAIT# output is enabled and brought to
High, WAIT# output keep High level until the end of burst or until the burst
operation is terminated.
When the device is operating in asynchronous mode, WAIT# output is always in
High Impedance.
102
128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004