S71WS512NE0BFWZZ Datasheet, PDF (80/142 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt

Advance Information
Synchronous/Burst Read @ V_IO = 1.8 V
Parameter
JEDEC Standard
Description
54 MHz 66 MHz Unit
t_IACC
t_BACC
t_ACS
t_ACH
t_BDH
t_CR
t_OE
t_CEZ
t_OEZ
t_CES
t_RDYS
t_RACC
t_AAS
t_AAH
t_CAS
t_AVC
t_AVD
t_CKA
t_CKZ
t_OES
t_RCC
Latency
Max
69
ns
Burst Access Time Valid Clock to Output Delay
Max
13.5
11.2
ns
Address Setup Time to CLK (Note 1)
Min
5
4
ns
Address Hold Time from CLK (Note 1)
Min
7
6
ns
Data Hold Time from Next Clock Cycle
Min
4
3
ns
Chip Enable to RDY Valid
Max
13.5
11.2
ns
Output Enable to Output Valid
Max
13.5
11.2
ns
Chip Enable to High Z
Max
10
8
ns
Output Enable to High Z
Max
10
8
ns
CE# Setup Time to CLK
Min
5
4
ns
RDY Setup Time to CLK
Min
5
4
ns
Ready Access Time from CLK
Max
13.5
11.2
ns
Address Setup Time to AVD# (Note 1)
Min
5
4
ns
Address Hold Time to AVD# (Note 1)
Min
7
6
ns
CE# Setup Time to AVD#
Min
0
ns
AVD# Low to CLK
Min
5
4
ns
AVD# Pulse
Min
12
10
ns
CLK to access resume
Max
13.5
11.2
ns
CLK to High Z
Max
10
8
ns
Output Enable Setup Time
Min
5
4
ns
Read cycle for continuous suspend
Max
1
ms
Notes:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
2. Clock Divider option
80
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004