S71WS512NE0BFWZZ Datasheet, PDF (124/142 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt

Preliminary
TIMING DIAGRAMS (Continued)
Asynchronous Read / Write Timing #1-1 (CE#1 Control)
t_WC
ADDRESS
CE#1
t_CHAH
t_AS
t_CP
WRITE ADDRESS
t_CW
t_WRC
t_ASC
t_CP
WE#
t_RC
READ ADDRESS
t_CE
t_CHAH
UB#, LB#
t_OHCL
OE#
t_CHZ
t_OH
t_DS
t_DH
t_CLZ
t_OH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
Notes *1: This timing diagram assumes CE2=H and ADV#=L.
*2: Write address is valid from either CE#1 or WE# of last falling edge.
Asynchronous Read / Write Timing #1-2 (CE#1 / WE# / OE# Control)
t_WC
t_RC
ADDRESS
CE#1
WE#
t_CHAH
t_AS
t_CP
WRITE ADDRESS
t_WR
t_ASC
t_CP
t_WP
READ ADDRESS
t_CE
t_CHAH
UB#, LB#
OE#
DQ
t_OHCL
t_CHZ
t_OH
t_DS
t_DH
t_OE
t_OLZ
t_OH
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Notes *1: This timing diagram assumes CE2=H and ADV#=L.
*2: OE# can be fixed Low during write operation if it is CE#1 controlled write at Read-Write-Read sequence.
124
128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004