MB84VD23581FJ-70 Datasheet, PDF (6/56 Pages) SPANSION – 64 M ( x 16) FLASH MEMORY & 64 M ( x 16) Mobile FCRAM

MB84VD23581FJ-70
s PIN DESCRIPTION
Pin Name
Function
A21 to A0
Address Inputs (Common)
DQ15 to DQ0 Data Inputs/Outputs (Common)
CEf
Chip Enable (Flash)
CE1r
Chip Enable (FCRAM)
CE2r
Chip Enable (FCRAM)
OE
Output Enable (Common)
WE
Write Enable (Common)
RY/BY
Ready/Busy Outputs (Flash) Open Drain Output
UB
Upper Byte Control (FCRAM)
LB
Lower Byte Control (FCRAM)
RESET
Hardware Reset Pin/Sector Protection Unlock (Flash)
WP/ACC
Write Protect/Acceleration (Flash)
PE
Partial Enable (FCRAM)
N.C.
No Internal Connection
VSS
Device Ground (Common)
VCCf
Device Power Supply (Flash)
VCCr
Device Power Supply (FCRAM)
s BLOCK DIAGRAM
A21 to A0
WP/ACC
RESET
CEf
A21 to A0
VCCf
VSS
64 M bit
Flash Memory
RY/BY
DQ15 to DQ0
PE
LB
UB
WE
OE
CE1r
CE2r
VCCr
VSS
A21 to A0
64 M bit
FCRAM
DQ15 to DQ0
Input/Output
I
I/O
I
I
I
I
I
O
I
I
I
I
I

Power
Power
Power
DQ15 to DQ0
5