MB84VP23481FK-70 Datasheet, PDF (23/67 Pages) SPANSION – 64M (X16) Page FLASH MEMORY & 32M (X16) Mobile FCRAMTM

MB84VP23481FK-70
*1: Both of these reset commands are equivalent.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET = VID.
*4: The valid addresses are A6 to A0.
*5: This command is valid during HiddenROM mode.
*6: The data “00h” is also acceptable.
*7: Data before fourth cycle also need to be programmed repearting from first cycle to third cycle.
*8: RD(0) of the sixth cycle shows PPB erase status. When RD(0) is "1", programming must be repeated
from the beginning of first cycle to the fourth cycle; both fifth and the sixth validate full completion of erase.
Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except for
PA, SA, BA, SGA, OPBP, SLA, PWA, PL, SPML, WP.
• Bus operations are defined in "s DEVICE BUS OPERATIONS".
• The system should generate the following address patterns:
555h or 2AAh to addresses A10 to A0
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• Command combinations not described in Command Definitions table are illegal.
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