COM20022I-3V Datasheet, PDF (81/83 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
b) Synchronize the Pre-Scalar Output
The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the
Setup1 register. The CKP3-1 bits are changed by writing the Setup1 register from outside the CPU.
It's not synchronized between the CPU and COM20022I 3V. Thus, changing the CKP2-0 timing does
not synchronize with the internal clocks of Pre-Scalar, and changing CKP2-0 may cause spike noise
to appear on the output clock line.
Setting the EF bit will include flip-flops inserted between the Setup1 register and Pre-Scalar for
synchronizing the CKP2-0 with Pre-Scalar’s internal clocks.
Never change the CKP2-0 when the data rate is over 5 Mbps. They must all be zero.
c) Shorten The Write Interval Time To The Command Register
The COM20022I 3V limits the write interval time for continuous writing to the Command register. The
minimum interval time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μS at the
156.25 Kbps. This 1.6 μS is very long for CPU.
Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to
XTAL clock which is not changed by the data rate, such that the minimum interval time becomes 100
nS.
d) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20022I 3V has a write prohibition period for writing the Enable Transmit/Receive
Commands. This period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition
period is caused by setting the TA/RI bit with an internal pulse signal. It is 3.2 μS at 156.25 Kbps.
This period may be a problem when using interrupt processing. The interrupt occurs when the RI bit
returns to High. The CPU writes the next Enable Receive Command to the other page immediately.
In this case, the interval time between the interrupt and writing Command is shorter than 3.2 μS.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the internal pulse signal for
setting the TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 9.1 following.
SMSC COM20022I 3V
Page 81
DATASHEET
Revision 02-27-06