COM20022I-3V Datasheet, PDF (21/83 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
DREQ
nWR
DMAEN bit
minimum 4TARB
Writing Address
Pointer Low
TARB is the ARBITRATION Clock Period. It depends on the TOPR and
SLOW-ARB bit. TOPR is the period of operation clock frequency (output
of the clock multiplier). It depends on the CKUP1 and CKUP0 bits.
TARB = TOPR @ SLOW-ARB = 0
TARB = 2 TOPR @ SLOW-ARB = 1
Figure 5.3 - DREQ Pin First Assertion Timing for all DMA Modes
As an example of gating by cycle, in an ISA bus system, the Refresh period is 15μS. Continuous transfer
by DMA must be less than 15μS to prevent blocking by the Refresh cycle. A DMA cycle of consecutive
DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5μS. The Refresh
execution time is 500nS. This computes to 15μS - 2.5μS - 500nS = 12μS or 12 cycles. Therefore the
DREQ pin must be negated every 12 cycles. Figure 5.4 illustrates the rough timing of the Programmable-
Burst mode DMA transfer.
SMSC COM20022I 3V
Page 21
DATASHEET
Revision 02-27-06