COM20022I-3V Datasheet, PDF (31/83 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
REGISTER
BUS
CONTROL
MSB
W16
X
ITCEN/
RTRG
DMA
COUNT
TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
TC5/
TIM5/
CYC5
Note 6.1 This bit can be written and read.
READ
TC8/
RSYN/
GTTM
TC4/
TIM4/
CYC4
DMA-MD1 DMA-MD0
TC3/
TIM3/
CYC3
TC2/
TIM2/
CYC2
TCPOL
TC1/
TIM1/
CYC1
LSB
ADDR
DRQ-POL 07-5
TC0/
TIM0/
CYC0
07-6
Table 6.2 - Data Register at 16 Bit Access
REGISTER
BIT1 BIT1 BIT1 BIT1 BIT1 BIT1 BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT ADDR
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
DATA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
04
ADDR
00
MSB
RI/TR1
01
C7
02
RD-DATA
03
A7
04
D7
05
(R/W)*
06
RESET
07-0
07-1
07-2
TID7
NID7
P1-MODE
07-3
07-4
07-5
0
RBUS-
TMG
W16
0
C6
AUTO-
INC
A6
D6
0
CCHEN
TID6
NID6
FOUR
NAKS
0
0
0
07-6
TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
Table 6.3 - Write Register Summary
WRITE
0
DMA
EXCNAK
RECON
END
C5
C4
C3
C2
0
0
DMAEN
A10
A5
A4
A3
A2
D5
0
TXEN
TID5
NID5
0
0
CKUP1
ITCEN/
RTRG
TC5/
TIM5/
CYC5
D4
0
ET1
TID4
NID4
RCV-
ALL
0
CKUP0
TC8/
RSYN/
GTTM
TC4/
TIM4/
CYC4
D3
(R/W)
(Note 6.2)
ET2
TID3
NID3
CKP3
D2
SUB-AD2
BACK-
PLANE
TID2
NID2
CKP2
0
EF
DMA-
MD1
0
NO-
SYNC
DMA-
MD0
TC3/
TIM3/
CYC3
TC2/
TIM2/
CYC2
NEW
NEXTID
C1
A9
A1
D1
SUB- AD1
SUB-
AD1
TID1
NID1
CKP1
0
RCN-
TM1
TC-POL
TC1/
TIM1/
CYC1
LSB
TA/
TTA
C0
A8
A0/ SWAP
D0
SUB-
AD0
SUB-
AD0
TID0
NID0
SLOW-ARB
0
RCN-
TM0
DRQ-POL
TC0/
TIM0/
CYC0
REGISTER
INTERRUPT
MASK
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA*
SUBADR
CONFIG-
URATION
TENTID
NODEID
SETUP1
TEST
SETUP2
BUS
CONTROL
DMA
COUNT
SMSC COM20022I 3V
Page 31
DATASHEET
Revision 02-27-06