COM20022I-3V Datasheet, PDF (45/83 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
BIT
BIT NAME
3,2 DMA Transfer
Mode
SYMBOL
DMAMD1,
DMAMD0
DESCRIPTION
These bits select the data transfer mode of the DMA. These
transfer modes influence the timing of asserting/negating the
DREQ pin.
1 TC Polarity
0 DREQ Polarity
TCPOL
DRQPOL
DMAMD1 DMAMD0
Transfer Mode
0
0
Non-Burst (Default)
0
1
Burst
1
0
Programmable-Burst by Timer
1
1
Programmable-Burst by Cycle
Counter
This bit sets the Active polarity of TC pin.
TCPOL = 0: Active High (Default), TCPOL = 1 Active Low
This bit sets the Active polarity of DREQ pin.
DRQPOL = 0: Active High (Default), DRQPOL = 1 Active
Low
BIT
BIT NAME
7-0 Terminal Count
Timer Mode
Cycle Mode
Table 6.15 - DMA Count Register
SYMBOL
TC7-TC0
TIM7-TIM0
CYC7-
CYC0
DESCRIPTION
TC7-TC0: Used for non-burst or burst mode. These are the
lower 8 bits of the Terminal Count setting register. The MSB
(TC8) is in the Bus Control Register. The Terminal Count
setting range is from 1 to 512 counts (TC8 - TC0 all zeroes
means 512 counts).
TIM7-TIM0: Used for Programmable-Burst by Timer mode.
These bits are for setting the term of the continuous DMA
transfer. The time range is from 100nS to 25.6μS. The step is
100nS (TIM7-TIM0 all zeroes means 25.6μs).
CYC7-CYC0: Used for Programmable-Burst by Cycle mode.
These bits are for setting the term of the continuous DMA
transfer. The cycle range is from 2 to 256 cycles. CYC7-
CYC0 all zeroes means 256 cycles. (1 is illegal)
SMSC COM20022I 3V
Page 45
DATASHEET
Revision 02-27-06