LAN9218I_12 Datasheet, PDF(77/134 Page) SMSC Corporation – High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

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LAN9218I_12 Datasheet, PDF (77/134 Pages) SMSC Corporation – High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

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High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

Datasheet

5.3.9 HW_CFGâHardware Configuration Register

Offset:

74h

Size:

32 bits

Note: The transmitter and receiver must be stopped before writing to this register. Refer to Section

3.11.8, "Stopping and Starting the Transmitter," on page 51 and Section 3.12.4, "Stopping and

Starting the Receiver," on page 55 for details on stopping the transmitter and receiver.

BITS

DESCRIPTION

31-25 Reserved

24 AMDIX_EN Strap State. This read-only bit reflects the state of the

AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers

27.15 and 27.13

23-21 Reserved

16-19

15-3

Must Be One (MBO). This bit must be set to â1â for normal device

operation.

TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values

to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the

space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the

remaining space specified by TX_FIF_SZ. The minimum size of the TX

FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for

both TX data and TX commands.

The RX status and data FIFOs consume the remaining space, which is

equal to 16KB â TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for

Configurable FIFO Memory Allocation," on page 78 for more information.

Reserved

2 32/16-bit Mode. When set, the LAN9218i is set for 32-bit operation. When

clear, it is configured for 16-bit operation. This field is the value of the

D32/nD16 strap.

1 Soft Reset Time-out (SRST_TO). If a software reset is attempted when the

internal PHY is not in the operational state (RX_CLK and TX_CLK running),

the reset will not complete and the soft reset operation will time-out and this

bit will be set to a â1â. The host processor must correct the problem and

issue another soft reset.

0 Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset

generates a full reset of the MAC CSRâs. The SCSRâs (system command

and status registers) are reset except for any NASR bits. Soft reset also

clears any TX or RX errors (TXE/RXE). This bit is self-clearing.

Notes:

Â Do not attempt a soft reset unless the internal PHY is fully awake and

operational. After a PHY reset, or when returning from a reduced power

state, the PHY must be given adequate time to return to the operational

state before a soft reset can be issued. The internal RX_CLK and TX_CLK

signals must be running for a proper software reset. Please refer to

Section 6.8, "Reset Timing," on page 123 for details on PHY reset timing.

Â The LAN9218i must always be read at least once after power-up, reset,

or upon return from a power-saving state or write operations will not

function.

TYPE

R/W

DEFAULT

AMDIX

Strap

SMSC LAN9218i

DATASHEET

Revision 2.9 (03-01-12)

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