LAN9218I_12 Datasheet, PDF (122/134 Pages) SMSC Corporation – High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

6.7
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9218i will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9218i. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-
bit write. Note that address lines A[2:1] are still used when the LAN9218i is operating in 32-bit and 16-
bit mode. Address bits A[7:3] are ignored.
FIFO_SEL
A[2:1]
nCS, nWR
Data Bus
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
Table 6.8 TX Data FIFO Direct PIO Write Timing
SYMBOL
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
MIN
TYP
45
32
13
0
0
7
0
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
Revision 2.9 (03-01-12)
122
DATASHEET
SMSC LAN9218i