LAN9218I_12 Datasheet, PDF (30/134 Pages) SMSC Corporation – High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
Register, which is described in Section 5.3.17, "WORD_SWAP—Word Swap Control," on page 85. This
register affects how words on the data bus are written to or read from the Control and Status Registers
and the Transmit and Receive Data/Status FIFOs. Refer to Table 3.7, "Word Swap Control (16-bit
mode only)" below for more details. Whenever the LAN9218i transmits data from the Transmit Data
FIFO to the network, the low order word is always transmitted first, and when the LAN9218i receives
data from the network to the Receive Data FIFO, the low-order word is always received first.
This register only takes effect when the LAN9218i is configured to operate in 16-bit mode. In 32-bit
mode, this register is ignored and the upper data bits, D[31:16], are always mapped to the high-order
word, and the lower data bits, D[15:0] are always mapped to the low-order word.
Table 3.7 Word Swap Control (16-bit mode only)
ADDRESS
BYTE ORDER
A1 PIN
D[15:8]
D[7:0]
DESCRIPTION
Default Mode - Word Swap Register equal to 0x00000000 or any value other than 0xFFFFFFFF
A1 = 0
A1 = 1
Byte 1
Byte 3
Byte 0
Byte 2
When A1=0, D[15:0] is mapped to the low order
words of CSRs and FIFOs. When A1=1, D[15:0] is
mapped to the high-order words of CSRs and
FIFOs. Since low-order words are always
transmitted/received first, A1=0 data will always
precede A1=1 data.
Word Swap Mode - Word Swap Register equal to 0xFFFFFFFF
A1 = 0
A1 = 1
Byte 3
Byte 1
Byte 2
Byte 0
When A1=0, D[15:0] is mapped to the high order
words of CSRs and FIFOs. When A1=1, D[15:0] is
mapped to the low order words of CSRs and FIFOs.
In this case A1=1 data will always precede A1=0
data.
3.7
General Purpose Timer (GP Timer)
The General Purpose Timer is a programmable block that can be used to generate periodic host
interrupts. The resolution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from
set ‘1’ to cleared ‘0,’ the GPT_LOAD field is initialized to FFFFh. The GPT_CNT register is also
initialized to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any
time; e.g., before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in
the GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is
written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT
interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT
interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the
GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only
be cleared by writing a ‘1’ to the bit.
3.8
EEPROM Interface
The LAN9218i can optionally load its MAC address from an external serial EEPROM. If a properly
configured EEPROM is detected by the LAN9218i at power-up, hard reset or soft reset, the ADDRH
Revision 2.9 (03-01-12)
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DATASHEET
SMSC LAN9218i