LAN9218I_12 Datasheet, PDF (32/134 Pages) SMSC Corporation – High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support

High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
EEPROM Write
Idle
EEPROM Read
Idle
Write Data
Regis ter
Write
Command
Re gis te r
W r ite
Command
Regis ter
Busy Bit = 0
Read
Command
Regis ter
Read
Command
Re gis te r
Busy Bit = 0
Read Data
Re gis te r
Figure 3.2 EEPROM Access Flow Diagram
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
3.8.2.1
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
page 90 for E2P_CMD field settings for each command.
Revision 2.9 (03-01-12)
32
DATASHEET
SMSC LAN9218i