LAN9116_08 Datasheet, PDF (77/132 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.9 HW_CFG—Hardware Configuration Register
Offset:
74h
Size:
32 bits
This register controls the hardware configuration of the LAN9116 Ethernet Controller.
Note: The transmitter and receiver must be stopped before writing to this register. Refer to Section
3.12.8, "Stopping and Starting the Transmitter," on page 52 and Section 3.13.4, "Stopping and
Starting the Receiver," on page 56 for details on stopping the transmitter and receiver.
BITS DESCRIPTION
31-21 Reserved
20 Must Be One (MBO). This bit must be set to “1” for normal device
operation.
16-19
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for
Configurable FIFO Memory Allocation," on page 77 for more information.
15-3 Reserved
2 32/16-bit Mode. When set, the LAN9116 is set for 32-bit operation. When
clear, it is configured for 16-bit operation. This field is the value of the
D32/nD16 strap.
1 Soft Reset Time-out (SRST_TO). If a software reset is attempted when the
internal PHY is not in the operational state (RX_CLK and TX_CLK running),
the reset will not complete and the soft reset operation will time-out and this
bit will be set to a ‘1’. The host processor must correct the problem and
issue another soft reset.
0 Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset
generates a full reset of the MAC CSR’s. The SCSR’s (system command
and status registers) are reset except for any NASR bits. Soft reset also
clears any TX or RX errors (TXE/RXE). This bit is self-clearing.
Notes:
„ Do not attempt a soft reset unless the internal PHY is fully awake and
operational. After a PHY reset, or when returning from a reduced power
state, the PHY must be given adequate time to return to the operational
state before a soft reset can be issued. The internal RX_CLK and TX_CLK
signals must be running for a proper software reset. Please refer to
Section 6.8, "Reset Timing," on page 123 for details on PHY reset timing.
„ The LAN9116 must always be read at least once after power-up, reset, or
upon return from a power-saving state or write operations will not function.
TYPE
RO
R/W
R/W
RO
RO
RO
SC
DEFAULT
-
0
5h
-
-
0
0
5.3.9.1
Allowable settings for Configurable FIFO Memory Allocation
TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above. The user
must select the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the hardware
SMSC LAN9116
77
DATASHEET
Revision 1.5 (07-11-08)