LAN9116_08 Datasheet, PDF (121/132 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
6.6
PIO Writes
PIO writes are used for all LAN9116 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are
identical with the exception that D[31:16] are ignored during a 16-bit write.
A[7:1]
nCS, nWR
Data Bus
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Table 6.7 PIO Write Cycle Timing
SYMBOL DESCRIPTION
MIN
t_cycle
Write Cycle Time
165
t_csl
nCS, nWR Assertion Time
32
t_csh
nCS, nWR Deassertion Time
13
t_asu
Address Setup to nCS, nWR Assertion
0
t_ah
Address Hold Time
0
t_dsu
Data Setup to nCS, nWR Deassertion
7
t_dh
Data Hold Time
0
TYP
MAX UNITS
ns
ns
ns
ns
ns
ns
ns
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
SMSC LAN9116
121
DATASHEET
Revision 1.5 (07-11-08)