LAN9116_08 Datasheet, PDF (130/132 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

7.6
Clock Circuit
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
The LAN9116 can accept either a 25MHz crystal (preferred) or a 25 MHz clock oscillator (±50 PPM)
input. The LAN9116 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1 (pin
6). If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and
CLKIN should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40%
minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the LAN9116
crystal input/output signals (XTAL1, XTAL2). See Table 7.6, "LAN9116 Crystal Specifications" for crystal
specifications. Refer to SMSC Application Note AN10.7 - “Parallel Crystal Circuit Input Voltage Control”
and the LAN9116 Reference Schematic for additional information.
Table 7.6 LAN9116 Crystal Specifications
PARAMETER
Crystal Cut
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
Frequency Tolerance @ 25^oC
Frequency Stability Over Temp
Frequency Deviation Over Time
Total Allowable PPM Budget
Shunt Capacitance
Load Capacitance
Drive Level
Equivalent Series Resistance
Operating Temperature Range
LAN9116 XTAL1 Pin
Capacitance
LAN9116 XTAL2 Pin
Capacitance
SYMBOL
F_fund
F_tol
F_temp
F_age
C_O
C_L
P_W
R₁
MIN
NOM
MAX
AT, typ
Fundamental Mode
Parallel Resonant Mode
-
25.000
-
-
-
+/-50
-
-
+/-50
-
+/-3 to 5
-
-
-
+/-50
-
7 typ
-
-
20 typ
-
0.5
-
-
-
-
30
0
-
+70
-
3 typ
-
-
3 typ
-
UNITS NOTES
MHz
PPM
PPM
PPM
PPM
pF
pF
mW
Ohm
o_C
pF
Note 7.11
Note 7.11
Note 7.12
Note 7.13
Note 7.14
pF
Note 7.14
Note 7.11
The maximum allowable values for Frequency Tolerance and Frequency Stability are
application dependant. Since any particular application must meet the IEEE +/-50 PPM
Total PPM Budget, the combination of these two values must be approximately +/-45 PPM
(allowing for aging).
Note 7.12 Frequency Deviation Over Time is also reffered to as Aging.
Note 7.13 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
+/- 50 PPM.
Note 7.14
This number includes the pad, the bond wire and the lead frame. PCB capacitance is not
included in this value. The XTAL1 and XTAL2 pin and PCB capacitance values are
required to accurately calculate the value of the two external load capacitors. These two
external load capacitors determine the accuracy of the 25.000 MHz frequency.
Revision 1.5 (07-11-08)
130
DATASHEET
SMSC LAN9116