LAN9217_07 Datasheet, PDF (76/137 Pages) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
BITS
12
11
10
9
8
7
6
5
4
3
2-0
DESCRIPTION
Reserved
TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data
FIFO underruns.
TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data
FIFO is full, and another write is attempted.
TX Data FIFO Available Interrupt (TDFA). Generated when the TX data
FIFO available space is greater than the programmed level.
TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status
FIFO is full.
TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status
FIFO reaches the programmed level.
RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued
whenever a receive frame is dropped.
RX Data FIFO Level Interrupt (RDFL). Generated when the RX FIFO
reaches the programmed level.
RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status
FIFO is full.
RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status
FIFO reaches the programmed level.
GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s.
These interrupts are configured through the GPIO_CFG register.
TYPE
RO
R/WC
DEFAULT
-
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
000
Revision 1.8 (06-06-07)
76
DATASHEET
SMSC LAN9217