LAN9217_07 Datasheet, PDF(37/137 Page) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

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LAN9217_07 Datasheet, PDF (37/137 Pages) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

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16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

noted above, the host is required to check the READY bit and verify that it is set before attempting

any other reads or writes of the device.

Note 3.7 The host must only perform read accesses prior to the ready bit being set.

Once the READY bit is set, the LAN9217 is ready to resume normal operation. At this time the WUPS

field can be cleared.

3.9.2.2

D2 Sleep

In this state, as shown in Table 3.9, all clocks to the MAC and host bus are disabled and the PHY is

placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY

(Mode Control/Status register) must be set. This places the PHY in the Energy Detect mode. The

PM_MODE bits in the PMT_CTRL register must then be set to 10b. Upon setting the PM_MODE bits,

the LAN9217 will enter the D2 sleep state. The READY bit in PMT_CTRL is cleared when entering the

D2 state.

Note 3.8 If carrier is present when this state is entered detection will occur immediately.

If properly enabled via the ED_EN and PME_EN bits, the LAN9217 will assert the PME hardware

signal upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to

a 01b.

Note 3.9 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the

setting of PME_EN.

A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the

LAN9217 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host

is required to check the READY bit and verify that it is set before attempting any other reads or writes

of the device. Before the LAN9217 is fully awake from this state the EDPWRDOWN bit in register 17

of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit

until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9217 is ready to resume

normal operation. At this time the WUPS field can be cleared.

Device

BLOCK

PHY

MAC Power

Management

MAC and Host

Interface

Internal Clock

Table 3.9 Power Management States

(NORMAL OPERATION)

Full ON

(WOL)

Full ON

RX Power Mgmt. Block

OFF

(ENERGY DETECT)

Energy Detect Power-Down

OFF

Full ON

OFF

KEY

CLOCK ON

BLOCK DISABLED â CLOCK ON

FULL OFF

SMSC LAN9217

DATASHEET

Revision 1.8 (06-06-07)

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