LAN9217_07 Datasheet, PDF (12/137 Pages) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

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16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly
accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and
the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer
can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working
buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX
FIFOs for the host to access the data.
Receive and Transmit FIFOs
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a
conduit between the host interface and the MAC through which all transmitted and received data and
status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the
various transport and OS software stacks thus reducing or minimizing overrun conditions. Like the
MAC, the FIFOs have separate receive and transmit data paths. In addition, the RX and TX FIFOs are
configurable in size, allowing increased flexibility.
Interrupt Controller
The LAN9217 supports a single programmable interrupt. The programmable nature of this interrupt
allows the user the ability to optimize performance dependent upon the application requirement. Both
the polarity and buffer type of the interrupt pin are configurable for the external interrupt processing.
The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with
other devices. In addition, a programmable interrupt de-assertion interval is provided.
GPIO Interface
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the
LAN9217. It is accessible through the host bus interface via the CSRs. The GPIO signals can function
as inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also
be configured to trigger interrupts with programmable polarity.
Serial EEPROM Interface
A serial EEPROM interface is included in the LAN9217. The serial EEPROM is optional and can be
programmed with the LAN9217 MAC address. The LAN9217 can optionally load the MAC address
automatically after power-on reset, hardware reset, or soft reset.
Power Management Controls
The LAN9217 supports comprehensive array of power management modes to allow use in power
sensitive applications. Wake on LAN, Link Status Change and Magic Packet detection are supported
by the LAN9217. An external PME (Power Management Event) interrupt is provided to indicate
detection of a wakeup event.
General Purpose Timer
The general-purpose timer has no dedicated function within the LAN9217 and may be programmed to
issue a timed interrupt.
Revision 1.8 (06-06-07)
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DATASHEET
SMSC LAN9217