LAN9217_07 Datasheet, PDF (109/137 Pages) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
5.5
PHY Registers
The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC
via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers.
PHY Register Indexes are shown in Table 5.8, "LAN9217 PHY Control and Status Register".
Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of
the PHY Basic Control Register (Reset) is set.
INDEX
(IN DECIMAL)
0
1
2
3
4
5
6
17
18
27
29
30
31
Table 5.8 LAN9217 PHY Control and Status Register
PHY CONTROL AND STATUS REGISTERS
REGISTER NAME
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Mode Control/Status Register
Special Modes Register
Special Control/Status Indications
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
SMSC LAN9217
109
DATASHEET
Revision 1.8 (06-06-07)