LAN9217_07 Datasheet, PDF (104/137 Pages) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

5.4.4
16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
HASHH—Multicast Hash Table High Register
Offset:
Default Value:
4
00000000h
Attribute:
Size:
R/W
32 bits
The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the
destination address in the incoming frame is used to index the contents of the Hash table. The most
significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit
within the register. A value of 00000 selects Bit 0 of the Multicast Hash Table Lo register and a value
of 11111 selects the Bit 31 of the Multicast Hash Table Hi register.
If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All
Multicast” (MCPAS) bit is set (1), then all multicast frames are accepted regardless of the multicast hash
values.
The Multicast Hash Table Hi register contains the higher 32 bits of the hash table and the Multicast
Hash Table Low register contains the lower 32 bits of the hash table.
BITS
31-0
DESCRIPTION
Upper 32 bits of the 64-bit Hash Table
5.4.5 HASHL—Multicast Hash Table Low Register
Offset:
Default Value:
5
00000000h
Attribute:
Size:
R/W
32 bits
This register defines the lower 32-bits of the Multicast Hash Table. Please refer to Table 5.4.4,
"HASHH—Multicast Hash Table High Register" for further details.
BITS
31-0
DESCRIPTION
Lower 32 bits of the 64-bit Hash Table
Revision 1.8 (06-06-07)
104
DATASHEET
SMSC LAN9217