LAN9217_07 Datasheet, PDF (73/137 Pages) SMSC Corporation – 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Table 5.1 Direct Address Register Map (continued)
BASE ADDRESS
+ OFFSET
B4h
B8h - FCh
CONTROL AND STATUS REGISTERS
SYMBOL
E2P_DATA
RESERVED
REGISTER NAME
EEPROM Data
Reserved for future use
5.3.1 ID_REV—Chip ID and Revision
Offset:
50h
Size:
32 bits
This register contains the ID and Revision fields for this design.
DEFAULT
00000000h
-
BITS
DESCRIPTION
31-16 Chip ID. This read-only field identifies this design
15-0 Chip Revision
5.3.2 IRQ_CFG—Interrupt Configuration Register
TYPE
RO
RO
DEFAULT
117Ah
0000h
Offset:
54h
Size:
32 bits
This register configures and indicates the state of the IRQ signal.
BITS
31:24
23-15
14
13
12
DESCRIPTION
Interrupt Deassertion Interval (INT_DEAS). This field determines the
Interrupt Request Deassertion Interval in multiples of 10 microseconds.
Setting this field to zero causes the device to disable the INT_DEAS
Interval, reset the interval counter, and issue any pending interrupts. If a
new, non-zero value is written to this field, any subsequent interrupts will
obey the new setting.
Note: This field does not apply to the PME interrupt.
Reserved
Interrupt Deassertion Interval Clear (INT_DEAS_CLR). Writing a one
to this register clears the de-assertion counter in the IRQ Controller, thus
causing a new de-assertion interval to begin (regardless of whether or
not the IRQ Controller is currently in an active de-assertion interval).
Interrupt Deassertion Status (INT_DEAS_STS). When set, this bit
indicates that interrupts are currently in a deassertion interval, and will
not be delivered to the IRQ pin. When this bit is clear, interrupts are not
currently in a deassertion interval, and will be delivered to the IRQ pin.
Master Interrupt (IRQ_INT). This read-only bit indicates the state of the
internal IRQ line, regardless of the setting of the IRQ_EN bit, or the state
of the interrupt de-assertion function. When this bit is high, one of the
enabled interrupts is currently active.
TYPE
R/W
RO
SC
SC
RO
DEFAULT
0
-
0
0
0
SMSC LAN9217
73
DATASHEET
Revision 1.8 (06-06-07)