USB97C102 Datasheet, PDF (74/80 Pages) SMSC Corporation – Multi-Endpoint USB Peripheral Controller with Integrated 5 Port HUB

AEN
SA[x]
nIOR
SD[x]
nIOW/nIOR
t9
t8
t3
t1
t2
t10
t7
t4
t5
DATA VALID
t6
FIGURE 16 – 8051 IO READ CYCLE
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Table 123 – 8051 IO Read Timing Parameters
DESCRIPTION
MIN MAX EQUIATION
SA[x] and AEN Valid to nIOR Asserted
107
4t-60
nIOR Asserted to nIOR Deasserted
150
6t-100
nIOR Asserted to SA[x] Invalid
32
t-10
nIOR Asserted to Data Valid
0
Data Hold/Float from nIOR Deasserted
0
nIOR Asserted after nIOR Deasserted
32
t-10
nIOR Asserted after nIOW Deasserted
32
t-10
nIOR Asserted to AEN Valid
10
Data Valid to nIOR Deassereted
30
nIOR Deasserted to SD[x] tri-state
32
t-10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: Min and Max delays shown for 8051 clk of 24 MHz, to calculate typical timing delays for other clock
frequencies use Oscillator Equations, where t=1/fCLK.
CLOCKI
t1
t2
t2
FIGURE 17 - INPUT CLOCK TIMING
NAME
t1
t2
tr, tf
Table 124 - Input Clock Timing Parameters
DESCRIPTION
MIN
TYP
Clock Cycle Time for 24 MHz
41.67
Clock High Time/Low Time for 14.318 MHz 25/16.7
Clock Rise Time/Fall Time (not shown)
MAX
16.7/25
5
UNITS
ns
ns
ns
SMSC DS – USB97C102
Page 74
Rev. 03/23/2000