USB97C102 Datasheet, PDF (30/80 Pages) SMSC Corporation – Multi-Endpoint USB Peripheral Controller with Integrated 5 Port HUB

Table 37 - ISA Bus Status Register
BUS_STAT
(0x7F73 - RESET=0xXX)
ISA BUS STATUS REGISTER
BIT
NAME
R/W
DESCRIPTION
7
CH3RQ
R
Channel 3 DMA Request
0 = No Request Pending
1 = Request Pending
6
CH2RQ
R
Channel 2 DMA Request
0 = No Request Pending
1 = Request Pending
5
CH1RQ
R
Channel 1 DMA Request
0 = No Request Pending
1 = Request Pending
4
CH0RQ
R
Channel 0 DMA Request
0 = No Request Pending
1 = Request Pending
3
CH3TC
R
Channel 3 Terminal Count Reached
0 = No
1 = Yes
2
CH2TC
R
Channel 2 Terminal Count Reached
0 = No
1 = Yes
1
CH1TC
R
Channel 1 Terminal Count Reached
0 = No
1 = Yes
0
CH0TC
R
Channel 0 Terminal Count Reached
0 = No
1 = Yes
Note 1: Each bit in this register reflects the current value of the corresponding bit in the 8237 CH_STAT status
register.
Note 2: The 8237 clears bits 3..0 in the CH_STAT status register when the 8051 reads it through the ISA Bus I/O
Window.
Note 3: Reading the BUS_STAT register does not clear or otherwise affect the BUS_STAT register.
Note 4: The ISADMA bit in ISR_0 is latched high whenever any bit in BUS_STAT that is enabled in BUS_MASK
transitions from low to high.
Note 5: This register is intended (1) to provide a view into the status of the 8237 without having to assume control of
the ISA bus during DMA transfers, and (2) to provide a means for generating the ISADMA interrupt in ISR_0
which indicates that a DMA transfer has completed and that the 8051 should take control of the bus and
setup the 8237 for its next transfer. Bits 7-4 can be used to generate additional interrupt requests from the
DREQ pins, or simply to monitor channel request status by masking them.
SMSC DS – USB97C102
Page 30
Rev. 03/23/2000