USB97C102 Datasheet, PDF (20/80 Pages) SMSC Corporation – Multi-Endpoint USB Peripheral Controller with Integrated 5 Port HUB

Table 12 - Interrupt 0 Mask
IMR_0
(0x7F01- RESET=0xFF)
INTERRUPT 0 MASK REGISTER
BIT
NAME
R/W
DESCRIPTION
7
IRQ3
R/W External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
6
IRQ2
R/W External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
5
IRQ1
R/W External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
4
IRQ0
R/W External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
3
RX_PKT
R/W Received Packet MMU Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
2
TX_EMPTY R/W Transmit Queue Empty MMU Interrupt
0 = Enable Interrupt
1 = Mask Interrupt
1
TX_PKT
R/W Transmit Packet MMU Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
0
ISADMA
R/W ISADMA Status Change Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Table 13 - Interrupt 1 Source Register
ISR_1
(0x7F02- RESET=0x00)
INTERRUPT 1 SOURCE REGISTER
BIT
NAME
R/W
DESCRIPTION
[7:5]
Reserved
R/W Reserved
4
EOT
R/W 1 = The SIE returned to Idle State. Marks the end of each
transaction.
3
SOF
R/W 1 = When a Start of Frame token is correctly decoded.
Generated by the write strobe to the Frame Count register.
2
ALLOC
R/W 1 = MCU Software Allocation Request complete interrupt. This
interrupt is not generated for hardware (SIEDMA) allocation
requests.
1
RX_OVRN R/W 1 = A receive condition has occurred that will stop the current
receive buffer to not be processed. The SIE automatically
recovers from this condition after its cause has been alleviated
(e.g. any partially allocated packets will be released. See Note
2).
0
PWR_MNG R/W 1 = A wakeup or power management event in the WU_SRC_1
or WU_SRC_2 registers has gone active.
Note 1: The bits in this register are cleared by writing a ‘1’ to the corresponding bit.
Note 2: The RX_OVRN interrupt should be considered by firmware as a general Receive Overrun of the SIE,
meaning that a packet destined for the RAM buffer could not be received and was not acknowledged back to
the Host. The firmware should check to see if the RX Packet Number FIFO Register (RXFIFO) is full. If it is
empty, then there may be too many transmit packets queued for the device to receive anything, or the last
packet may have been corrupted on the wire. If it is not empty, then one or more receive packets must be
dequeued before the device can continue to receive packets. In the normal course of operation, the MCU
should respond to a RX_PKT interrupt as often as possible and let the buffering logic do its job.
Note 3: The RX_OVRN Interrupt can also be triggered if a non-isochronous packet exceeds 64 bytes or if an
isochronous packet exceeds the programmed limit (SIE_CTRL2 – Page 58). When a packet that is too long
is detected, the packet will be discarded from memory and the RX Overrun Interrupt will be triggered. For
non-isochronous packets, the hardware will stall the Rx Endpoint at the handshake after reception.
SMSC DS – USB97C102
Page 20
Rev. 03/23/2000