USB97C102 Datasheet, PDF (60/80 Pages) SMSC Corporation – Multi-Endpoint USB Peripheral Controller with Integrated 5 Port HUB

Endpoints 0-7. The MCU will write these registers, and set the corresponding bit=1 for each endpoint that is a non-
control endpoint. The hardware will not respond to a Setup PID for any endpoint whose corresponding bit is set (1).
Table 108 - NonControl Endpoint Register 1 (high endpoints)
NONCTRL_EP1
(0x7FAB – RESET=0x00)
NONCONTROL ENDPOINT REGISTER 1
BIT
NAME
R/W
DESCRIPTION
7
EP15
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID
6
EP14
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID
5
EP13
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID
4
EP12
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID
3
EP11
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID
2
EP10
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID
1
EP9
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID
0
EP8
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID
Table 109 - NonControl Endpoint Register 2 (low endpoints)
NONCTRL_EP2
(0x7FAC – RESET=0x00)
NONCONTROL ENDPOINT REGISTER 2
BIT
NAME
R/W
DESCRIPTION
7
EP7
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID.
6
EP6
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID.
5
EP5
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID.
4
EP4
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID.
3
EP3
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID.
2
EP2
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID.
1
EP1
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID.
0
EP0
R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.
When this bit is cleared (0), the Endpoint will respond to a setup PID.
RESERVED
BIT
NAME
[7:0] Reserved
Table 110 – Reserved
RESERVED
R
DESCRIPTION
R Reserved
The Memory Management Policy (MMP) feature permits limiting the number of received packets in memory per
endpoint. A five bit up/down counter will be implemented for each endpoint. Each counter will be incremented by the
MCU to initialize the limit, then decremented by the hardware as packets arrive at its corresponding endpoint, and
incremented by the MCU after it releases the packet. If the count reaches 0, and the MMP feature is enabled, then
the hardware will not receive the packet and will NAK non-isochronous OUT tokens. If the count is zero, it will not
decrement further; if the count is 31, it will not increment further. The MCU can enable or disable this feature
independently for each endpoint. The default condition is disabled.
SMSC DS – USB97C102
Page 60
Rev. 03/23/2000