LAN9211_12 Datasheet, PDF (63/147 Pages) SMSC Corporation – High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
3.13.2
RX Packet Format
The RX status words can be read from the RX status FIFO port, while the RX data packets can be
read from the RX data FIFO. RX data packets are formatted in a specific manner before the host can
read them as shown in Figure 3.26. It is assumed that the host has previously read the associated
status word from the RX status FIFO, to ascertain the data size and any error conditions.
Host Read
Order
1st
2nd
Last
31
0
Optional offset DWORD0
.
.
Optional offset DWORDn
ofs + First Data DWORD
.
.
.
.
Last Data DWORD
Optional Pad DWORD0
.
.
Optional Pad DWORDn
Figure 3.26 RX Packet Format
Figure 3.27 shows the RX packet format when the RX checksum is enabled. The RX checksum data
appended to the data payload is treated just as an additional 4-bytes within the RX Data FIFO. The
RX checksum is enabled by setting the RXCOE_EN bit in the COE_CR—Checksum Offload Engine
Control Register. For more information on the RX checksum, refer to Section 3.6.1, "Receive
Checksum Offload Engine (RXCOE)".
SMSC LAN9211
63
DATASHEET
Revision 2.9 (03-01-12)