LAN9211_12 Datasheet, PDF (147/147 Pages) SMSC Corporation – High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
Table 9.1 Customer Revision History (continued)
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY
CORRECTION
Rev. 2.3
(08-18-08)
Rev. 2.2
(06-19-08)
Rev. 2.2
(06-10-08)
Rev. 2.1
(05-13-08)
Rev. 2.0
(04-11-08)
Rev. 1.92
(10-22-07)
Note 7.6 on page 142
Note following I/O Buffer Characteristics table
modified:
Changed from: ".....the per-pin input leakage is 10
divided by the maximum input leakage current."
to: ".....the per-pin input leakage is the maximum
input leakage current divided by 10."
Figure 1.2, "Internal Block
Diagram"
Diagram redone.
The word “Core” was added to the regulator block
title.
Table 2.4, “System and
Changed VDD_CORE/VDD18CORE bulk
Power Signals,” on page 17 ^{capacitor value from 10uF to 4.7uF.}
Auto-negotiation
Bits 9 and 15 relabeled as Reserved, Read-Only
Advertisement on page 119 (RO), with a default of 0.
Auto-negotiation
Advertisement on page 119
Fixed definition of bits 11:10 when equal to “11” by
adding “advertise support for..” to beginning of
definition. Also added note stating “When both
symmetric PAUSE and asymmetric PAUSE
support are advertised, the device will only be
configured to, at most, one of the two settings
upon auto-negotiation completion.”
Section 3.5, "Wake-up
Frame Detection," on
page 25 and Section 5.4.1,
"MAC_CR—MAC Control
Register," on page 105
Added note: “When wake-up frame detection is
enabled via the WUEN bit of the WUCSR—Wake-
up Control and Status Register, a broadcast wake-
up frame will wake-up the device despite the state
of the Disable Broadcast Frame (BCAST) bit in the
MAC_CR—MAC Control Register.”
Section 5.4.12,
"WUCSR—Wake-up Control
and Status Register," on
page 114
Fixed typo in bit 9: “... Mac Address [1:0] bit set to
0.” was changed to “...Mac Address [0] bit set to 0.”
Section 3.6.1.1, "RX
Checksum Calculation," on
page 31
“checksum = [B0, B1] + C0 + [B2, B3] + C1 + …
+ [0, BN] + CN-1” changed to “checksum = [B1,
B0] + C0 + [B3, B2] + C1 + … + [0, BN] + CN-1”
Table 7.3 on page 140
Added 1.8V Analog Supply Current (VDD_A18)
into the VDD_IO supply current and removed the
1.8V row.
Section 1.1, "Block
Diagram"
Removed the system memory block and arrow
above the microprocessor/ microcontroller
Section 7.6, "DC Electrical Input leakage current values added
Specifications," on page 141
Chapter 2 Pin Description
and Configurationon
page 14
Pin assignment information re-organized into
separate table.
Transmit Checksum Offload
Engine (TXCOE) section of
Chapter 3, "Functional
Description," on page 21.
Note added indicating the proper usage of the TX
checksum preamble (DWORD alignment).
EECLK pin description in
Chapter 2 Pin Description
and Configurationon
page 14
Note added to EECLK pin description to indicate
proper usage.
SMSC LAN9211
147
DATASHEET
Revision 2.9 (03-01-12)