LAN9211_12 Datasheet, PDF (28/147 Pages) SMSC Corporation – High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

3.6
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9211 is in the D0 or D1
power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the
D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when
the device enters the D1 state.
Checksum Offload Engines (COE)
The LAN9211 contains two checksum offload engines, which offload the calculation of the 16-bit
checksum for transmitted and received Ethernet frames. The functionality of the checksum offload
engines is described in the following sections:
„ Receive Checksum Offload Engine (RXCOE)
„ Transmit Checksum Offload Engine (TXCOE)
3.6.1
Receive Checksum Offload Engine (RXCOE)
The receive checksum offload engine provides assistance to the CPU by calculating a 16-bit checksum
for a received Ethernet frame. The RXCOE readily supports the following IEEE802.3 frame formats:
„ Type II Ethernet frames
„ SNAP encapsulated frames
„ Support for up to 2, 802.1q VLAN tags
The resulting checksum value can also be modified by software to support other frame formats.
The RXCOE has two modes of operation. In mode 0, the RXCOE calculates the checksum between
the first 14 bytes of the Ethernet frame and the FCS. This is illustrated in Figure 3.2.
DST
T
SRC
Y
P
E
Frame Data
Calculate Checksum
Figure 3.2 RXCOE Checksum Calculation
Revision 2.9 (03-01-12)
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SMSC LAN9211