LAN9211_12 Datasheet, PDF (11/147 Pages) SMSC Corporation – High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
1.2
Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal
Block Diagram".
+3.3V
25MHz
EEPROM
(Optional)
PME
Wakup Indicator
Power
Management
16-bit SRAM I/F
Host Bus Interface
(HBI)
PIO Controller
IRQ
FIFO_SEL
Interrupt
Controller
GP Timer
3.3V to 1.8V
Core Regulator
2kB to 14kB
Configurable TX FIFO
TX Status FIFO
RX Status FIFO
2kB to 14kB
Configurable RX FIFO
PLL
EEPROM
Controller
RX Checksum
Offload Engine
TX Checksum
Offload Engine
10/100
Ethernet
MAC
MIL - RX Elastic
Buffer - 128 bytes
MIL - TX Elastic
Buffer - 2K bytes
10/100
Ethernet ^LAN
PHY
1.3
1.4
Figure 1.2 Internal Block Diagram
10/100 Ethernet PHY
The LAN9211 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in
either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance
especially in full duplex mode. The data paths connect to the PIO interface Function via separate
busses to increase performance. Payload data as well as transmit and receive status is passed on
these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is
accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent
Interface) port internal to the LAN9211. The MAC CSR's also provide a mechanism for accessing the
PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly
accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and
the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer
SMSC LAN9211
11
DATASHEET
Revision 2.9 (03-01-12)