COM20022I_06 Datasheet, PDF (62/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
AD0-AD2,
D3-D15
nCS
VALID
t1
t2,
t4
VALID DATA
ALE
nWR
nRD
nIOCS16
t3
t9
t5
t13 ^{Note 3}
t14
Previous Value
t15
Invalid
t10
t6
t11
t7
Note 2
t8**
t12
t8
Valid Value
MUST BE: BUSTMG pin = HIGH
Parameter
min
max units
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nDS Low
t6 Valid Data Setup to nDS High
t7 Data Hold from nDS High
t8 Cycle Time (nWR to Next )**
t9 _{ALE High Width}
t10 ALE Low Width
t11 nWR Low Width
t12 nWR High Width
t13 nRD to nWR Low
t14 nIOCS16 Hold Delay from ALE Low
t15 nIOCS16 Output Delay from ALE Low
20
nS
10
nS
10
nS
10
nS
15
nS
30
nS
10
nS
4TARB*
nS
20
nS
20
nS
20
nS
20
nS
20
nS
0
nS
40
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
** Note 2: _{Any cycle occurring after a write to Address Pointer Low Register requires a}
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
Revision 02-27-06
Page 62
DATASHEET
SMSC COM20022I