COM20022I_06 Datasheet, PDF (31/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
REGISTER
STATUS
MSB
RI/TRI
Table 6.1 - Read Register Summary
READ
X/RI
X/TA
POR
TEST RECON
DIAG.
STATUS
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA*
SUB ADR
MY-
RECON
RD-
DATA
A7
D7
(R/W)*
DUPID
AUTO-
INC
A6
D6
0
RCV-
ACT
X
A5
D5
0
TOKEN
X
A4
D4
0
CONFIG-
URATION
TENTID
NODE ID
SETUP1
NEXT ID
SETUP2
BUS
CONTROL
RESET CCHEN TXEN
TID7
NID7
P1
MODE
NXT
ID7
RBUS-
TMG
W16
TID6
NID6
FOUR
NAKS
NXT
ID6
X
X
TID5
NID5
X
NXT
ID5
CKUP1
ITCEN/
RTRG
DMA
COUNT
TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
TC5/
TIM5/
CYC5
Note*: This bit can be written and read.
ET1
TID4
NID4
RCV-
ALL
NXT
ID4
CKUP0
TC8/
RSYN/
GTTM
TC4/
TIM4/
CYC4
EXC-
NAK
DMA-
EN
A3
D3
(R/W)*
ET2
TID3
NID3
CKP3
NXT
ID3
EF
DMA-
MD1
TC3/
TIM3/
CYC3
TENTID
A10
A2
D2
SUB-
AD2
BACK-
PLANE
TID2
NID2
CKP2
NXT
ID2
NO-
SYNC
DMA-
MD0
TC2/
TIM2/
CYC2
TMA
NEW
NEXTID
A9
A1
D1
SUB-
AD1
SUB-
AD1
TID1
NID1
CKP1
NXT
ID1
RCN-
TM1
TCPOL
TC1/
TIM1/
CYC1
LSB
TA/
TTA
X
A8
A0/
SWAP
D0
SUB-
AD0
SUB-
AD0
TID0
NID0
SLOW-
ARB
NXT
ID0
RCM-
TM2
DRQ-
POL
TC0/
TIM0/
CYC0
ADDR
00
01
02
03
04
05
06
07-0
07-1
07-2
07-3
07-4
07-5
07-6
*DATA REGISTER AT 16 BIT ACCESS
REGISTER
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT _ADDR
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DATA
D
D
D
D
D
D D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
04
15 14 13 12 11 10
SMSC COM20022I
Page 31
DATASHEET
Revision 02-27-06