COM20022I_06 Datasheet, PDF (60/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
AD0-AD2,
D3-D15
nCS
ALE
nRD
VALID
t1
t2,
t4
t3
t9
t6
t5
VALID DATA
t10
t7
nWR
nIOCS16
Previous Value
t13 Note 3
t15
t14
Invalid
t8
t11
Valid Value
t12
Note 2
MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0
Parameter
min
max units
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nRD Low
t6 nRD Low to Valid Data
t7 nRD High to Data High Impedance
t8 Cycle Time (nRD Low to Next Time Low)
t9 ALE High Width
t10 ALE Low Width
t11 nRD Low Width
t12 nRD High Width
t13 nWR to nRD Low
t14 nIOCS16 Hold Delay from ALE Low
t15 nIOCS16 Output Delay from ALE Low
20
nS
10
nS
10
nS
10
nS
15
nS
40
nS
0
20
nS
4TARB*
nS
20
nS
20
nS
60
nS
20
nS
20
nS
0
nS
40
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
Revision 02-27-06
Page 60
DATASHEET
SMSC COM20022I