COM20022I_06 Datasheet, PDF (3/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Table of Contents
Chapter 1 General Description................................................................................................................ 6
Chapter 2 Pin Configuration.................................................................................................................... 7
Chapter 3 Description of Pin Functions .................................................................................................. 8
Chapter 4 Protocol Description ............................................................................................................. 11
4.1 Network Protocol ........................................................................................................................................11
4.2 Data Rates .................................................................................................................................................11
4.2.1 Selecting Clock Frequencies Above 2.5 Mbps....................................................................................12
4.3 Network Reconfiguration ............................................................................................................................12
4.4 Broadcast Messages..................................................................................................................................13
4.5 Extended Timeout Function .......................................................................................................................13
4.5.1 Response Time ...................................................................................................................................13
4.5.2 Idle Time .............................................................................................................................................13
4.5.3 Reconfiguration Time ..........................................................................................................................13
4.6 Line Protocol ..............................................................................................................................................14
4.6.1 Invitations To Transmit........................................................................................................................14
4.6.2 Free Buffer Enquiries ..........................................................................................................................14
4.6.3 Data Packets.......................................................................................................................................14
4.6.4 Acknowledgements .............................................................................................................................15
4.6.5 Negative Acknowledgements ..............................................................................................................15
Chapter 5 System Description .............................................................................................................. 16
5.1 Microcontroller Interface.............................................................................................................................16
5.1.1 Selection of 8/16-Bit Access ...............................................................................................................19
5.1.2 DMA Transfers To And From Internal RAM ........................................................................................19
5.1.3 DMA Operation ...................................................................................................................................20
5.1.4 DMA Data Transfer Sequence (I/O to Memory: Read A Packet) ........................................................24
5.1.5 DMA Data Transfer Sequence (Memory to I/O: Write A Packet).........................................................24
5.1.6 High Speed CPU Bus Timing Support ................................................................................................24
5.2 Transmission Media Interface ....................................................................................................................25
5.2.1 Traditional Hybrid Interface .................................................................................................................26
5.2.2 Backplane Configuration .....................................................................................................................26
5.2.3 Differential Driver Configuration ..........................................................................................................28
5.2.4 Programmable TXEN Polarity .............................................................................................................28
Chapter 6 Functional Description.......................................................................................................... 30
6.1 Microsequencer..........................................................................................................................................30
6.2 Internal Registers .......................................................................................................................................32
6.2.1 Interrupt Mask Register (IMR) .............................................................................................................32
6.2.2 Data Register ......................................................................................................................................33
6.2.3 Tentative ID Register ..........................................................................................................................33
6.2.4 Node ID Register.................................................................................................................................33
6.2.5 Next ID Register..................................................................................................................................34
6.2.6 Status Register....................................................................................................................................34
6.2.7 Diagnostic Status Register ..................................................................................................................34
6.2.8 Command Register .............................................................................................................................34
6.2.9 Address Pointer Registers ..................................................................................................................34
6.2.10 Configuration Register.....................................................................................................................35
6.2.11 Sub-Address Register .....................................................................................................................35
6.2.12 Setup 1 Register..............................................................................................................................35
6.2.13 Setup 2 Register..............................................................................................................................35
6.3 Bus Control Register ..................................................................................................................................36
6.4 DMA Count Register ..................................................................................................................................36
6.5 Internal RAM ..............................................................................................................................................47
6.5.1 Sequential Access Memory.................................................................................................................47
6.5.2 Access Speed .....................................................................................................................................47
6.6 Software Interface ......................................................................................................................................47
6.6.1 Selecting RAM Page Size ...................................................................................................................48
6.6.2 Transmit Sequence .............................................................................................................................49
6.6.3 Receive Sequence ..............................................................................................................................50
SMSC COM20022I
Page 3
DATASHEET
Revision 02-27-06