COM20022I_06 Datasheet, PDF(43/82 Page) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

COM20022I_06 Datasheet, PDF (43/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

◁

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

BIT

BIT NAME

7 Pulse1 Mode

6 Four NACKS

5 Reserved

4 Receive All

3,2,1 Clock Prescaler Bits

3,2,1

0 Slow Arbitration

Select

Table 6.10 - Setup 1 Register

SYMBOL

P1MODE

FOUR

NACKS

RCVALL

CKP3,2,1

DESCRIPTION

This bit determines the type of PULSE1 output driver used in

Backplane Mode. When high, a push/pull output is used. When

low, an open drain output is used. The default is open drain.

This bit, when set, will cause the EXNACK bit in the Diagnostic

Status Register to set after four NACKs to Free Buffer Enquiry are

detected by the COM20022I. This bit, when reset, will set the

EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default

is 128.

Do not set.

This bit, when set, allows the COM20022I to receive all valid data

packets on the network, regardless of their destination ID. This

mode can be used to implement a network monitor with the

transmitter on- or off-line. Note that ACKs are only sent for

packets received with a destination ID equal to the COM20022I's

programmed node ID. This feature can be used to put the

COM20022I in a 'listen-only' mode, where the transmitter is

disabled and the COM20022I is not passing tokens. Defaults low.

These bits are used to determine the data rate of the COM20022I.

The following table is for a 20 MHz crystal: (Clock Multiplier is

bypassed)

CKP3 CKP2 CKP1 DIVISOR

SPEED

2.5Mbs

1.25Mbs

625Kbs

312.5Kbs

128

156.25Kbs

Note: The lowest data rate achievable by the COM20022I is

156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock Multiplier

output clock speed greater than 20 MHz, CKP3, CKP2 and

CKP1 must all be zero.

SLOWARB

This bit, when set, will divide the arbitration clock by 2. Memory

cycle times will increase when slow arbitration is selected.

Note: For clock multiplier output clock speeds greater than 40

MHz, SLOWARB must be set. Defaults to low.

SMSC COM20022I

Page 43

DATASHEET

Revision 02-27-06

▷