LAN8187_06 Datasheet, PDF (32/72 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM

±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR^TM
Datasheet
Table 4.4, “Boot Strapping Configuration Resistors,” on page 32) to VSS to set the device in
TX_ER/TXD4 mode. The default setting is high (nINT mode).
4.11
PHY Address Strapping and LED Output Polarity Selection
The PHY ADDRESS bits are latched on the rising edge of the internal reset (nreset). The 5-bit address
word[0:4] is input on the LED1, LED2, LED3, LED4, GPO1 output pins. The default setting is all high
5'b1_1111.
The address lines are strapped as defined in the diagram below. The LED outputs will automatically
change polarity based on the presence of an external pull-down resistor. If the LED pin is pulled high
(by an internal 100K pull-up resistor) to select a logical high PHY address, then the LED output will
be active low. If the LED pin is pulled low (by an external pull-down resistor (see Table 4.4, “Boot
Strapping Configuration Resistors,” on page 32) to select a logical low PHY address, the LED output
will then be an active high output.
To set the PHY address on the LED pins without LEDs or on the GPO1 or CRS pin, float the pin to
set the address high or pull-down the pin with an external resistor (see Table 4.4, “Boot Strapping
Configuration Resistors,” on page 32) to GND to set the address low. See the figure below:
Phy Address = 1
LED output = active low
VDD
Phy Address = 0
LED output = active high
LED1-LED4
~10K ohms
~270 ohms
~270 ohms
LED1-LED4
4.12
4.12.1
Figure 4.5 PHY Address Strapping on LED’s
Variable Voltage I/O
The Digital I/O pins on the LAN8187/LAN8187I are variable voltage to take advantage of low power
savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.6V up to
+3.6V. Due to this low voltage feature addition, the system designer needs to take consideration as
for two aspects of their design. Boot strapping configuration and I/O voltage stability.
Boot Strapping Configuration.
Due to a lower I/O voltage, a lower strapping resistor needs to be used to ensure the strapped
configuration is latched into the PHY device at power-on reset.
Table 4.4 Boot Strapping Configuration Resistors
I/O voltage Pull-up/Pull-down Resistor
3.0 to 3.6 ^{10k ohm resistor}
2.0 to 3.0 ^{7.5k ohm resistor}
SMSC LAN8187/LAN8187I
32
DATASHEET
Revision 1.0 (12-14-06)